Clock signals are commonly used in many electronics circuits for various purposes. For example, clock signals are used to trigger synchronous circuits (e.g., flip-flops) in digital circuits such as processors, memory devices, and so on. Clock signals may be generated with various types of oscillators and supporting circuitry.
A clock signal continually transitions between logic high and logic low. The clock signal has a duty cycle that is determined by the time duration at logic high and the time duration at logic low. It is desirable to generate the clock signal to have a duty cycle that is as close to 50% as possible, so that the logic high duration is close to the logic low duration. A digital circuit may use both the rising and falling edges of the clock signal to trigger synchronous circuits to achieve faster operating speed. A 50% duty cycle for the clock signal may then provide the synchronous circuits with maximum timing margins.
The duty cycle of a clock signal may be distorted due to various phenomena such as mismatches in transistor devices used to generate the clock signal. Great care is often used in designing clock generation and distribution circuits to minimize device mismatches. Unfortunately, as device size shrinks in advanced integrated circuit (“IC”) process technologies, duty cycle distortion due to random variations and device mismatches becomes worse. Furthermore, digital circuits fabricated with advanced IC processes typically operate at high speed, e.g., one gigahertz (“GHz”) or higher. The high speed corresponds to a smaller clock period, e.g., 1 nanosecond (“nsec”) for 1 GHz. Small circuit mismatches may then translate to a relatively large error in duty cycle with the smaller clock period.
In order to correct for the error in the duty cycle, an IC typically has a detection circuit for precisely determining that error. Next, a duty cycle correction circuit can adjust the duty cycle to compensate for the error such that the duty cycle reaches the ideal 50 percent duty cycle or close to it as possible. Duty cycle detection can be performed in many ways. Some techniques involve converting high and low times to frequencies and then comparing the frequencies of the high and low times. This requires a complicated mechanism and long process times to improve the accuracy. Therefore, there exists a need for new techniques to efficiently and correctly determine a duty cycle of a clock signal.